The present invention relates to a digital circuit for synchronizing a pulse train.
A digital circuit of this kind is disclosed in the published European Patent Application EP No. 43 407 A2.*.sup.) It serves to synchronize a pulse train obtained as the output signal of the presettable frequency divider for a clock signal whose frequency is at least one order of magnitude higher than that of the pulse train. The pulse train is synchronized with horizontal synchronizing pulses contained in a received standard television signal which, after being demodulated in the television receiver, is present as the composite color signal and which is fed to an analog-to-digital converter clocked by a clock signal. The divisor of the frequency divider is set depending on the phase difference between the pulse train and the horizontal synchronizing pulses which is averaged over an averaging time equal to a major number of periods of the horizontal synchronizing pulses. FNT *.sup.) corresponding to U.S. Ser. No. 276,573 filed June 23, 1981, abandoned and U.S. Ser. No. 509,979 filed June 30, 1983, now U.S. Pat. No. 4,471,299.
In the arrangement of the above identified application, the resolution of the digital phase measurement is determined by the frequency of the clock signal and can be increased by the averaging, which can be implemented with a digital filter, only for a limited period of time. However, phase errors whose rate of change lies above the cutoff frequency of the filter can only be measured with the accuracy of one clock-signal period. During the horizontal synchronization of television receivers with digital signal-processing circuitry, where the clock frequency is usually four times the frequency of the chrominance subcarrier and where such a clock signal is used as in the present invention and in the above identified application, it is necessary to have a higher phase resolution than that given by the period of the clock signal.